1. Field of the Invention
The invention relates generally to digital electronic systems, more particularly, to an architecture for a control store of a Central Processing Unit (CPU).
2. Description of the Relevant Art
Digital system designers are continually attempting to maximize the speed of computer systems and circuits. One particular system of interest is a CPU control store which stores control information in the form of microinstructions. One, or more, microinstructions are executed to implement one machine (macro) instruction.
The memory elements utilized in the control store are characterized by an access time. The magnitude of this access time may restrict the speed of operation of the CPU.
One method of overcoming this speed restriction is to utilize an interleaved memory system. Several slow memory banks are grouped so that every sequential fetch comes from the next memory bank. Thus, the access time for a given instruction overlaps the readout time of the previous instruction.
The various banks of an interleaved memory system may be implemented on a single random access memory (RAM) or on multiple RAMs. Typically, the address (ADR) space of the instruction set is distributed over the memory banks. For example, the nth instruction may be stored at ADR(n) in a given memory bank and the (n+1)th instruction may be stored at ADR(n) in the succeeding memory bank. In this example, one memory bank stores even lines of microcode and the other memory bank stores odd lines of microcode. This distribution of the address space over the memory banks either requires restrictions on the possible branches in the instruction set or reduces the speed of execution of the branches.
Another problem inherent in the use of a control store is the occurrence of soft or hard errors in the instruction set. Generally, upon detecting errors the control store access system must either halt or implement an error correction routine that takes many machine cycles to complete. This error correction function degrades the speed of operation of the CPU.
Accordingly, a control store that allows for fast access to an instruction set is needed in highspeed computer systems. Further, the ability of the control store to quickly correct for hard or soft errors in an instruction is greatly needed.